1. Field of the Invention
The present invention relates to a semiconductor integrated circuit layout method and in particular, to a semiconductor device capable of improving cooling efficiency with a high integration density and reducing electric resistance as well as increasing the assembling efficiency.
2. Description of the Prior Art
Conventionally, there have been suggested various semiconductor devices capable of improving cooling efficiency with a high integration density. For example, Japanese Patent Publication 58-114500 discloses a semiconductor device as shown in FIG. 6. In FIG. 6, on each of unit substrates 41, a semiconductor device 42 connected to a lead 43 is mounted. The units substrates are arranged in matrix shape (honeycomb shape) and the leads between the unit substrates are connected to each other via connectors (not depicted). In space 44 between the unit substrates thus assembled, coolant is flown so as to cool the semiconductor device 42.
Moreover, Japanese Patent Publication 6-342991 discloses a semiconductor device as shown in FIG. 7. In FIG. 7, prolonged main body substrates 51 having a hexagonal end face are bundled and semiconductor devices 52 are mounted on the outer exposed surface. On the hexagonal surface of the main body substrates 51, a lead 53 is formed to be connected to the semiconductor device 52. Moreover, leads 53 of the adjacent substrates are connected in contact with each other. And coolant is flown through a hollow center 54 of the prolonged main body substrate 51 so as to cool the semiconductor device 52.
In the conventional technique shown in FIG. 6, coolant is flown inside and the semiconductor device can be cooled down. However, leads are used for connection between the semiconductor devices, which increases electric resistance. Moreover, a plenty of unit substrates are assembled to form a space for flowing the coolant and connectors are used for connection between the unit substrates. Thus, a plenty of assembling steps are required. Furthermore, since each semiconductor device is mounted separately, the number of assembling steps is further increased.
On the other hand, in the conventional technique as shown in FIG. 7, the coolant flown inside can cool down the semiconductor device. However, in the same way as in FIG. 6, since leads are used for connection between the semiconductor devices, the electric resistance is increased. Moreover, since each semiconductor device is separately mounted, the number of assembling steps is increased. Furthermore, the semiconductor devices are mounted only on the outer exposed surface of the bundled main body substrates and accordingly, it is impossible to realize a higher integration density.
It is therefore an object of the present invention to provide a semiconductor device capable of sufficiently cooling the semiconductor device, reducing the electric resistance, realizing a high integration density, and reducing the number of assembling steps.
It is therefore an object of the present invention to provide a semiconductor device capable of sufficiently cooling the semiconductor device, reducing the electric resistance, realizing a high integration density, and reducing the number of assembling steps.
The present invention provides a semiconductor device comprising: a tape wiring substrate; a semiconductor device mounted on one main side of the tape wiring substrate; a solder ball or bump electrode electrically connected with a predetermined position of the one main side of the tape wiring substrate including the semiconductor device and provided on the other side of the tape wiring substrate; and a hollow pipe-shaped substrate; wherein the tape wiring substrate is wound on the hollow pipe-shaped substrate with the one main side directed to the hollow pipe-shape substrate.